The present invention relates to a control circuit for an output power transistor (low-side driver) having means for reducing and controlling switching delays and which permits to make the turn-off and the turn-on delays of the output signal substantially identical.
Many power ICs are required to drive toward ground external loads connected to a supply line (low-side driver). The power switch that is commonly employed in these ICs, whenever the fabrication technology will permit it, is an--integrated DMOS transistor, because it offers numerous advantages as compared with a bipolar transistor of similar power rating.
By driving the gate of the DMOS, its drain voltage Vd (which is equal to drain/source voltage Vds when the source is grounded), i.e. the voltage (signal) on the output node of the low-side driver stage, varies between Vds=Rdson*Id and Vds=H.V., wherein Rdson is the resistance of the power transistor when it is conducting, Id is the drain current flowing through the power transistor, and H.V. is the supply voltage of the external load.
In order to minimize the power dissipated through the power transistor when it is conducting, it is necessary to minimize its Rdson. This is obtained by applying to the gate a voltage higher than the grounded source potential of the power transistor by a well defined quantity, equal to about 10 V (overdrive voltage). Most often in practice, the supply voltage Vcc of the integrated circuit is applied to the gate of the output power transistor during a conduction phase.
A control circuit that is normally used for driving an output power DMOS transistor is schematically depicted in FIG. 1.
The current generators I1 and I2, driven by the switching signals S1 and S2 in phase opposition to each other, have the function of charging and discharging, respectively, the capacitance of the driving node (gate) of the power DMOS. FIG. 2 shows the time-diagram of the gate and drain voltages of the power transistor during a turn-on phase and during a turn-off phase. Three distinct operating regions of the characteristics may be observed in both phases.
During a turn-on, in a first zone I of the characteristic, the gate voltage rises from Vgs=0 V to Vgs=Vth (threshold voltage). In this region of the characteristic, there isn't any flow of current through the power transistor and the current I1 charges the gate capacitance: Cgs+Cgd.
In a second region II of the characteristic, the output power transistor starts to conduct, its drain voltage drops from Vds=H.V. to Vds=Von=Rdson*Id while the current I1 continues to charge the gate capacitance which in this phase is given by Cgs+Cgd(Vds/Vgs), where the term: Cgd(Vds/Vgs) is due to the so-called Miller effect. In this zone of the characteristic, also referred to as the saturation zone, the gate voltage does not change much because the contribution to the input capacitance due to the Miller effect is preponderant in respect to the physical capacitance Cgs between gate and source of the transistor.
In a third zone III, also known as the "triode operation" zone, the output power transistor is fully on, its input capacitance having been charged completely, up to the maximum driving voltage (Vcc). In this region, the drain voltage Vds does not change much. Vcc represents the overdrive voltage that serves to minimize the Rdson of the power transistor.
The interval of time, during which the transistor functions in the second zone II of the characteristic curve, determines the so-called fall time (tf) of the output signal, present on the drain node of the output transistor while the interval of time, during which the transistor functions in the zone I of the characteristics curve, defines the so-called turn-on delay time (tphl) as referred to an input signal.
The behavior of the output DMOS in a "turn-off" phase is similar to its behavior during a "turn-on" phase. That is, the gate capacitance discharges through three distinct phases. The duration of the first zone I' defines a turn-off delay time (tplh) and the interval of time during which the transistor functions in the second zone II' during a turn-off phase determines a rise time (tr).
From a qualitative analysis of the switching phases of the power DMOS, it may be concluded that the rise time (tr) is equal to the fall time (tf) if I1=I2, while the turn-off (tplh) and turn-on delays (tphl), as referred to a driving (input) signal, are different from each other.
This is due to the fact that, in order to bring the DMOS to an on state (at the start of the saturation zone II) the variation of the gate voltage will be: .DELTA.Vgs1=Vth, while in order to pass from the so-called "triode" operation zone to the zone where the Miller effect occurs, the variation of the gate voltage will be: .DELTA.Vgs2=(Vcc-Vgson), where Vgson is the gate voltage at which the DMOS may be considered to be fully on. If the generators I1 and I2 have the same value, by being .DELTA.Vgs2&gt;.DELTA.Vgs1, the turn-off delay time results greater than the turn-on delay time.
In many practical applications of the circuit, it is often required that the output signal, i.e. the drain voltage (Vds) of the output power transistor, have a "length" identical to the "length" of the driving signal. This requires concurrence of both conditions: tr=tf and tphl=tplh.